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Project:HM55B: Difference between revisions

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174 bytes removed ,  3 September 2010
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  \[/_\/_\/_\/_\&:10]
  \[/_\/_\/_\/_\&:10]


RAW3WIRE>\[/_\/_\/_\/_\&:10]
The delay may not be needed.
CLOCK, 0
CS ENABLED
CLOCK, 1
DATA OUTPUT, 0
CLOCK, 0
CLOCK, 1
DATA OUTPUT, 0
CLOCK, 0
CLOCK, 1
DATA OUTPUT, 0
CLOCK, 0
CLOCK, 1
DATA OUTPUT, 0
CLOCK, 0
DELAY 0b00001010uS
CS DISABLED
 


Take sample (1100 is the response for success, 00xx is for incomplete, xx11 is error, see p9 of datasheet)
Take sample (1100 is the response for success, 00xx is for incomplete, xx11 is error, see p9 of datasheet)
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Note that &:50000 isn't enough of a delay, but && works, presumably because BusPirate parser adds a huge delay.  This means that we don't know how fast this module can be clocked, because each ! will be > 50ms apart.
Note that &:50000 isn't enough of a delay, but && works, presumably because BusPirate parser adds a huge delay.  This means that we don't know how fast this module can be clocked, because each ! will be > 50ms apart.
We could test this with:


Sample values:
Sample values:
3,313

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