Project:HM55B: Difference between revisions
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[http://www.parallax.com/dl/docs/prod/compshop/HM55BModDocs.pdf Datasheet] | [http://www.parallax.com/dl/docs/prod/compshop/HM55BModDocs.pdf Datasheet] | ||
== Bus Pirate pinout == | |||
From http://dangerousprototypes.com/docs/Bus_Pirate_101_tutorial | |||
<pre> | |||
Pin name Description (Bus Pirate is the master) | |||
MOSI Master data out, slave in (SPI, JTAG), Serial data (1-Wire, I2C, KB), TX* (UART) | |||
CLK Clock signal (I2C, SPI, JTAG, KB) | |||
MISO Master data in, slave out (SPI, JTAG) RX (UART) | |||
CS* Chip select (SPI), TMS (JTAG) | |||
AUX Auxiliary IO, frequency probe, pulse-width modulator | |||
ADC Voltage measurement probe (max 6volts) | |||
Vpu Voltage input for on-board pull-up resistors (0-5volts). | |||
+3.3v +3.3volt switchable power supply | |||
+5.0v +5volt switchable power supply | |||
GND Ground, connect to ground of test circuit | |||
</pre> | |||
== Testing with the BusPirate == | == Testing with the BusPirate == | ||
Revision as of 22:26, 9 December 2010
About the module
$20-25 compass module for embedded systems. SMD will be cheaper.
Bus Pirate pinout
From http://dangerousprototypes.com/docs/Bus_Pirate_101_tutorial
Pin name Description (Bus Pirate is the master) MOSI Master data out, slave in (SPI, JTAG), Serial data (1-Wire, I2C, KB), TX* (UART) CLK Clock signal (I2C, SPI, JTAG, KB) MISO Master data in, slave out (SPI, JTAG) RX (UART) CS* Chip select (SPI), TMS (JTAG) AUX Auxiliary IO, frequency probe, pulse-width modulator ADC Voltage measurement probe (max 6volts) Vpu Voltage input for on-board pull-up resistors (0-5volts). +3.3v +3.3volt switchable power supply +5.0v +5volt switchable power supply GND Ground, connect to ground of test circuit
Testing with the BusPirate
Settings:
- M (mode)
- 8 (3-wire raw)
- 4 (400KHz)
- 2 (3.3V high)
- W (turn on 5V output)
Reset
\[/_\/_\/_\/_\&:10]
The delay may not be needed.
Take sample
1100 is the response for success, 00xx is for incomplete, xx11 is error, see p9 of datasheet)
\[/-\/_\/_\/_\&&]&:10[&:10/-\/-\/_\/_\!!!!&!!!!!!!!!!!&!!!!!!!!!!!]
READ BIT: 1 READ BIT: 1 READ BIT: 0 READ BIT: 0 DELAY 0b00000001uS READ BIT: 0 READ BIT: 0 READ BIT: 0 READ BIT: 0 READ BIT: 0 READ BIT: 0 READ BIT: 1 READ BIT: 0 READ BIT: 0 READ BIT: 0 READ BIT: 0 DELAY 0b00000001uS READ BIT: 1 READ BIT: 1 READ BIT: 1 READ BIT: 1 READ BIT: 1 READ BIT: 1 READ BIT: 1 READ BIT: 1 READ BIT: 1 READ BIT: 0 READ BIT: 0
Note that &:50000 isn't enough of a delay, but && works, presumably because BusPirate parser adds a huge delay. This means that we don't know how fast this module can be clocked, because each ! will be > 50ms apart.
The BusPirate wiki suggests this will work (since we've determined that it still provides the 22 sample bits even if the reading is incomplete):
\[0b0000 &] [0b1000 && ]&[& 0b1100 r:4]
Sample readings:
0,-6
-1,-11
-1,-19
