OccupyWireless/ceedtec ppc26.cfg
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Revision as of 17:05, 3 February 2012 by Samthetechie (talk | contribs) (Created page with "<pre> ;bdiGDB configuration file for Sandpoint 8240 evaluation system ;-------------------------------------------------------------- ; [INIT] ; init core register ; init core re...")
;bdiGDB configuration file for Sandpoint 8240 evaluation system ;-------------------------------------------------------------- ; [INIT] ; init core register ; init core register WREG MSR 0x00000000 ;clear MSR ; begin fast memory config WM32 0xFEC00000 0x80000080 ;select MSAR1 WM32 0xFEE00000 0x00204060 ; WM32 0xFEC00000 0x84000080 ;select MSAR2 WM32 0xFEE00000 0x80a0c0e0 ; WM32 0xFEC00000 0x90000080 ;select MEAR1 WM32 0xFEE00000 0x1f3f5f7f ; WM32 0xFEC00000 0x94000080 ;select MEAR2 WM32 0xFEE00000 0x9fbfdfff ; WM32 0xFEC00000 0xa0000080 ;select MBEN WM8 0xFEE00000 0x03 ; WM32 0xFEC00000 0xa0000080 ;select MPM (PGMAX) WM8 0xFEE00003 0x15 ; WM32 0xFEC00000 0xf0000080 ;select MCCR1 WM32 0xFEE00000 0x00006088 ;do not set MEMGO WM32 0xFEC00000 0xf4000080 ;select MCCR2 WM32 0xFEE00000 0xe00f0000 ; WM32 0xFEC00000 0xf8000080 ;select MCCR3 WM32 0xFEE00000 0x000000c4 ; WM32 0xFEC00000 0xfc000080 ;select MCCR4 WM32 0xFEE00000 0x2133b023 ; Enable EXT_ROM WM32 0xFEC00000 0x76000080 ;select MIOCR1 WM8 0xFEE00000 0x04 ;Enable DLL_MAX_DELAY WM32 0xFEC00000 0xf0000080 ;select MCCR1 WM32 0xFEE00000 0x00006888 ;now set MEMGO ; WM32 0xFEC00000 0x78000080 ;select EUMBBAR WM32 0xFEE00000 0x000000fc ;Embedded utility memory block at 0xFC000000 ; end fast memory config WM32 0xFEC00000 0x78000080 ;select EUMBBAR WM32 0xFEE00000 0x000000fc ;Embedded utility memory block at 0xFC000000 ; end slow memory config ; WM32 0xFEC00000 0xa8000080 ;select PICR1 WM32 0xFEE00000 0x901014ff ;enable flash write (Flash on processor bus) ; ; Added to use the high drive strength for the memory selects & addressing ;WM32 0xFEC00000 0x70000080 ; select ODCR ;WM8 0xFEE00003 0xff ; high drive for everything ; ; Added to toggle the DLL_RESET bit WM32 0xFEC00000 0xe0000080 ; select AMBOR WM8 0xFEE00000 0xe0 ; DLL_RESET on WM32 0xFEC00000 0xe0000080 ; select AMBOR WM8 0xFEE00000 0xc0 ; DLL_RESET off ; ; define maximal transfer size TSZ4 0xFF800000 0xFFFFFFFF ;ROM space (only for Local bus flash) [TARGET] CPUTYPE 8240 32BIT ;the CPU type (603EV,750,8240,8260) JTAGCLOCK 0 ;use 16 MHz JTAG clock BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT | GATEWAY) BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoint MMU XLAT ;linux kernel MMU translation DCACHE NOFLUSH ;data cache flushing (FLUSH | NOFLUSH) PTBASE 0x000000f0 ;Use kernel with MMU support [HOST] IP 192.168.0.200 FILE /umbra/ppcboot FORMAT BIN LOAD MANUAL ;load code MANUAL or AUTO after reset DEBUGPORT 2001 [FLASH] ; Am29LV800BB on local processor bus (RCS0) ; set PPMC8240 switch SW2-1 OFF => ROM on Local bus ; enable flash write in PICR1 (see INIT part) ; set maximal transfer size to 4 bytes (see INIT part) CHIPTYPE AM29BX8 ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16) CHIPSIZE 0x800000 ;The size of one flash chip in bytes (e.g. Am29LV800BB = 0x100000) BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64) WORKSPACE 0x00020000 ;workspace in SDRAM ;;Enable this to flash ppcboot FORMAT BIN 0xfff00000 ;Image format FILE /umbra/ppcboot ;The file to program ;End of ppcboot section ;;Enable this to flash the kernel image FORMAT BIN 0xff810000 ;Image format FILE /umbra/zImage ;The file to program ;;End of kernel-ramdisk section ;;Enable this to flash the ramdisk image FORMAT BIN 0xff940000 ;Image format FILE /umbra/ramdisk ;The file to program ;;End of kernel-ramdisk section ;Ramdisk ERASE 0xFF940000 ERASE 0xFF950000 ERASE 0xFF960000 ERASE 0xFF970000 ERASE 0xFF980000 ERASE 0xFF990000 ERASE 0xFF9a0000 ERASE 0xFF9b0000 ERASE 0xFF9c0000 ERASE 0xFF9d0000 ERASE 0xFF9e0000 ERASE 0xFF9f0000 ERASE 0xFFa00000 ERASE 0xFFa10000 ERASE 0xFFa20000 ERASE 0xFFa30000 ERASE 0xFFa40000 ERASE 0xFFa50000 ERASE 0xFFa60000 ERASE 0xFFa70000 ERASE 0xFFa80000 ERASE 0xFFa90000 ERASE 0xFFaa0000 ERASE 0xFFab0000 ERASE 0xFFac0000 ERASE 0xFFad0000 ERASE 0xFFae0000 ERASE 0xFFaf0000 ERASE 0xFFb00000 ERASE 0xFFb10000 ERASE 0xFFb20000 ERASE 0xFFb30000 ERASE 0xFFb40000 ERASE 0xFFb50000 ERASE 0xFFb60000 ERASE 0xFFb70000 ERASE 0xFFb80000 ERASE 0xFFb90000 ERASE 0xFFba0000 ERASE 0xFFbb0000 ERASE 0xFFbc0000 ERASE 0xFFbd0000 ERASE 0xFFbe0000 ERASE 0xFFbf0000 ERASE 0xFFc00000 ERASE 0xFFc10000 ERASE 0xFFc20000 ERASE 0xFFc30000 ERASE 0xFFc40000 ERASE 0xFFc50000 ERASE 0xFFc60000 ERASE 0xFFc70000 ERASE 0xFFc80000 ERASE 0xFFc90000 ERASE 0xFFca0000 ERASE 0xFFcb0000 ERASE 0xFFcc0000 ERASE 0xFFcd0000 ERASE 0xFFce0000 ERASE 0xFFcf0000 ERASE 0xFFd00000 ERASE 0xFFd10000 ERASE 0xFFd20000 ERASE 0xFFd30000 ERASE 0xFFd40000 ERASE 0xFFd50000 ERASE 0xFFd60000 ERASE 0xFFd70000 ERASE 0xFFd80000 ERASE 0xFFd90000 ERASE 0xFFda0000 ERASE 0xFFdb0000 ERASE 0xFFdc0000 ERASE 0xFFdd0000 ERASE 0xFFde0000 ERASE 0xFFdf0000 ERASE 0xFFe00000 ERASE 0xFFe10000 ERASE 0xFFe20000 ERASE 0xFFe30000 ERASE 0xFFe40000 ERASE 0xFFe50000 ERASE 0xFFe60000 ERASE 0xFFe70000 ERASE 0xFFe80000 ERASE 0xFFe90000 ERASE 0xFFea0000 ERASE 0xFFeb0000 ERASE 0xFFec0000 ERASE 0xFFed0000 ERASE 0xFFee0000 ERASE 0xFFef0000 ;; [REGS] DMM1 0xFC000000 ;Embedded utility memory base address IMM1 0xFEC00000 0xFEE00000 ;configuration registers at byte offset 0 IMM2 0xFEC00000 0xFEE00001 ;configuration registers at byte offset 1 IMM3 0xFEC00000 0xFEE00002 ;configuration registers at byte offset 2 IMM4 0xFEC00000 0xFEE00003 ;configuration registers at byte offset 3 FILE /bdi/reg8240.def