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Project:HM55B: Difference between revisions

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A delay is required between starting the measurement and shifting in the status flag:
A delay is required between starting the measurement and shifting in the status flag:


  \[/_\/_\/_\/_\][/-\/_\/_\/_\][/-\/-\/_\/_\&&&&&&!!!!!!!!!!!!!!!!!!!!!!!!!!]
  \[/_\/_\/_\/_\][/-\/_\/_\/_\][/-\/-\/_\/_\&&&&&&&&!!!!!!!!!!!!!!!!!!!!!!!!!!]


Note that &&&&&& works but &:6 does not, even though the nominal value in both cases is the same, presumably because BusPirate parser adds a huge delay.  This means that we don't know how fast this module can be clocked, because each ! will be > 50ms apart.
Note that &&&&&&&& works but &:8 does not, even though the nominal value in both cases is the same, presumably because BusPirate parser adds a huge delay.  This means that we don't know how fast this module can be clocked, because each ! will be > 50ms apart.
 
The minimum required delay was 6us, 7us and 8us in three modules tested so, in production, as per data sheet, it would be a question of starting a measurement and polling status flag till 0b1100 was received.


The [http://dangerousprototypes.com/docs/SPI BusPirate wiki] suggests this will work (since we've determined that it still provides the 22 sample bits even if the reading is incomplete):
The [http://dangerousprototypes.com/docs/SPI BusPirate wiki] suggests this will work (since we've determined that it still provides the 22 sample bits even if the reading is incomplete):


  \[0b0000 &]
  \[0b0000 &][0b1000 && ]&[& 0b1100 r:4]
[0b1000 && ]&[& 0b1100 r:4]


=== Exiting ===
=== Exiting ===
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